Flash memory devices have developed into a popular source of non-volatile memory for a wide range of electronic applications. Flash memory devices typically use a one-transistor memory cell that allows for high memory densities, high reliability, and low power consumption. Common uses for flash memory include personal computers, flash drives, digital cameras, and cellular telephones. Program code and system data such as a basic input/output system (BIOS) are typically stored in flash memory devices for use in personal computer systems.
A flash memory is a type of memory that can be erased and reprogrammed in blocks instead of one byte at a time. A typical flash memory comprises a memory array that includes a large number of memory cells. Changes in threshold voltage of the memory cells, through programming of charge storage nodes (e.g., floating gates or charge traps) or other physical phenomena (e.g., phase change or polarization), determine the data value of each cell. The cells are typically grouped into blocks. Each of the cells within a block can be electrically programmed, such as by charging the charge storage node. The data in a cell of this type is determined by the presence or absence of the charge in the charge storage node. The charge can be removed from the charge storage node by an erase operation.
In a NAND architecture memory device, the memory blocks can be organized as series strings of memory cells, such as illustrated in FIG. 1. Each series string can be comprised of a number of flash memory cells 100 (e.g., 32) coupled serially drain-to-source between a select gate drain (SGD) transistor 101 and a select gate source (SGS) transistor 102.
The SGD/SGS transistors 101, 102 can be formed of the same type of transistors as the flash memory cells 100. Since the SGD/SGS transistors 101, 102 initially behave the same as the flash memory cells 100, the SGD/SGS transistors 101, 102 can be programmed and erased as well. Thus, prior to initial use of the memory device, the SGD/SGS transistors 101, 102 should be programmed to a particular threshold voltage to enable proper operation of each series string of memory cells. The transistors 101, 102 can subsequently be turned on whenever that threshold voltage is applied to the transistor's control gate.
The control gates of the SGD transistors 101 are common across all of the series strings of a memory block. Similarly, the control gates of the SGS transistors 102 are common across all of the series strings the memory block. Thus, a programming voltage applied to an SGD control gate of one series string of memory cells is also applied to the remaining SGD control gates of other series strings in the same memory block. This is also true of the SGS transistors.
Once a particular SGD/SGS transistor has been programmed and has passed program verify, that particular transistor should be program inhibited. The program inhibit prevents over-programming of the programmed SGD/SGS transistor from additional programming pulses applied to other SGD/SGS transistors, of the same memory block, that have not yet passed program verify.
For the reasons stated above, and for other reasons stated below that will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a way to inhibit select gate transistors during a programming operation.